The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to an electrically erasable programmable read-only memory (EEPROM) device for increasing the coupling ratio.
Memory devices are largely divided into volatile memory devices in which stored information can be erased and new information can be stored, and non-volatile memory devices in which the stored information can generally be retained permanently.
As the volatile memory devices, there are random-access memories (RAMs) that allow information writing as well as information reading. As the non-volatile memory devices, there are read-only memories (ROMs), erasable programmable ROMs (EPROMs) and electrically erasable programmable ROMs (EEPROMs).
Among the non-volatile memory devices, the ROMs are devices in which programming cannot be performed again if information is stored therewith once. The EPROMs and EEPROMs are devices which can erase the stored information and be programmed again to store new information.
In the EPROMs and EEPROMs, the operation of programming an information is the same, but the methods for erasing the stored information are different from each other.
In other words, the EPROMs erase the stored information with ultraviolet (UV) light, while the EEPROMs erase the stored information electrically.
Among these memory devices, the EEPROMs will be described below.
A conventional EEPROM semiconductor memory device having an "ETOX" (EPROM Tunneling Oxide) will be described below with reference to the attached drawings.
FIGS. 1a to 1c are cross-sectional views illustrating a method for manufacturing a conventional EEPROM memory device. FIGS. 2a and 2b are schematic view illustrating operations for programming and erasing data in the conventional EEPROM memory device.
As shown in FIG. 1c, a floating gate 3a and a control gate 5a are stacked on a P-type silicon substrate 1. As a source region and a drain region, first and second impurity regions 7 and 8 are formed in the P-type silicon substrate 1 on both sides of the floating gate 3a.
Here, between the P-type silicon substrate 1 and the floating gate 3a, and between the floating gate 3a and the control gate 5a, insulating films are formed.
Between the floating gate 3a and the control gate 5a, an insulating film 4 is formed with a thickness corresponding to a gate insulating film of a general transistor. Between the floating gate 3a and the P-type silicon substrate 1, a thin tunnel oxide film 2 is formed.
A method for manufacturing such a conventional EEPROM device will be described below.
As shown in FIG. 1a, on a P-type silicon substrate 1, a tunnel oxide film 2, a first polysilicon 3, an insulating film 4 and a second polysilicon 5 are deposited sequentially.
As shown in FIG. 1b, a photoresist film 6 is deposited on the second polysilicon 5. Then, through exposure and development process, a control gate region and a floating gate region are defined.
As shown in FIG. 1c, using the defined photoresist film 6 as a mask, the second polysilicon 5, insulating film 4, first polysilicon 3 and tunnel oxide film 2 are selectively removed to form a control gate 5a and a floating gate 3a.
Then, using the control gate 5a and floating gate 3a as a mask, n-type impurity ions of high concentration are implanted into the P-type silicon substrate 1, thereby forming first and second impurity regions 7 and 8.
The operation of the conventional EEPROM device having the ETOX is as follows.
In order to write data into one cell, as shown in FIG. 2a, a voltage of 7.about.8V is applied to the second impurity region 8. A voltage pulse of 12.about.13V is applied to the control gate 5a, and the first impurity region 7 and P-type silicon substrate 1 are grounded. Then, a high energy is created from the PN junction formed between the n-type second impurity region 8 and the P-type silicon substrate 1, thereby causing a breakdown. Due to the breakdown, hot electrons are generated.
Some of the hot electrons have energy higher than the energy barrier height (about 2.3V) between the P-type silicon substrate 1 and the tunnel oxide film 2. Thus, some of the hot electrons are injected into the floating gate 3a from the P-type silicon substrate 1 through the tunnel oxide film 2, and stored therein. Such a method is called the channel hot electron injection method. This results in a cell having a logic "1" state in the binary system.
Referring to FIG. 2b, in order to erase the data written in the cell by the above described method, the P-type silicon substrate 1 and control gate 5a are grounded. A voltage pulse of 12.about.13V is applied to the first impurity region 7. Then, through the portion of the thin tunnel oxide film 2 where the floating gate 3a overlaps the first impurity region 7, the electrons are discharged from the floating gate 3a into the first impurity region 7 by Fowler-Nordheim tunneling. Fowler-Nordheim tunneling dominantly occurs when the thickness of a tunneling oxide (e.g. tunnel oxide film 2) is below about 4-5 nm and the applied voltage is high. Fowler-Nordheim tunneling allows the electrons to be injected into the conduction band of the tunneling oxide by tunneling and thus into the impurity region.
At this time, as the quantity of electrons discharging from the floating gate 3a is increased gradually, the threshold voltage of the cell becomes low gradually. In general, erasing of the stored data is carried out so that the threshold voltage of the cell is maintained at 3V or less.
Accordingly, a logic "0" state is provided in the binary system.
In the EEPROM device having the conventional ETOX, a random access is possible when reading a data. Thus, the time required for reading the data can be relatively short.
The EEPROM device having the conventional ETOX has the coupling ratio (KW) as follows. The coupling ratio represents a voltage in the floating gate induced by an external voltage applied to the control gate. Therefore, the greater the capacitance between the control gate and the floating gate, the greater the coupling ratio will be. ##EQU1##
Here, C1 represents the capacitance between the control gate 5a and the floating gate 3a,
C2 represents the capacitance between the source and the floating gate 3a, PA1 C3 represents the capacitance between the substrate 1 and the floating gate 3a, and PA1 C4 represents the capacitance between the drain and the floating gate 3a. During erasing, the coupling ratio is as follows. ##EQU2## PA1 Cr=C1+C2+C3+C4, PA1 Vcg represents the control gate voltage, PA1 Vb represents the drain voltage, PA1 Vsub represents the substrate voltage, and PA1 Vs represents the source voltage.
Further, a program voltage Vp for the EEPROM is as follows. ##EQU3##
Here, Qfg represents the charge of the floating gate 3a,
According to the above equations, it is desirable to have a high coupling ratio so that effective programming can be carried out. To obtain the high coupling ratio, the capacitance between the control gate and the floating gate should be increased. By increasing the cell size, the capacitance between the control gate and the floating gate can be increased. But, increasing the cell size causes a great difficulty in high density device packing.
Therefore, in the conventional EEPROMs, a high voltage must be applied to the drain in an attempt to compensate for the low coupling ratio. As a result, the conventional EEPROMs have problems in that they consume high power and are less reliable for effective programming.